1. Field of The Invention
The present invention relates to a semiconductor device which incorporates a semiconductor integrated circuit chip for use in electronic equipment, such as a computer. More specifically, the present invention relates to a semiconductor device in which a decoupling capacitor for power supply use is arranged in close proximity with a semiconductor integrated circuit chip in order to stabilize operation of the semiconductor integrated circuit chip at high frequencies.
2. Description of the Related Art
A decoupling capacitor (or bypass capacitor) is commonly used with the semiconductor integrated circuit (IC) chip to reduce the noise in the power supplied to the IC chip. Advances in IC technology have increased the switching speeds employed by the recent IC devices, so that many IC chips are capable of operation at high frequencies, or microwave frequencies. High switching speeds increase the problem of power supply noise, a component of which is generated as the device is switched on and off. In order for the IC chip to function properly, the power supplied must be free from noise.
Use of the decoupling capacitor to alleviate the problem of power supply noise is well known. It is also well known that it is desirable to position the decoupling capacitor as close as possible to the IC chip for best effect. The leads connecting the capacitor to the IC chip have an inherent inductance which becomes significant at high speed operation, to the point that if the capacitor is positioned too far from the IC chip, the lead inductance can cancel the usefulness of the capacitor for eliminating power supply noise.
In a semiconductor device in which decoupling capacitors are arranged near a semiconductor integrated circuit (IC) chip as preventive measures against malfunctioning of the IC chip due to power supply noise at high frequencies, multi-layered chip capacitors have often been used as the decoupling capacitors.
FIG. 1 shows the structure of a semiconductor device in which multi-layered chip capacitors are mounted.
In the semiconductor device of FIG. 1, the semiconductor IC chip 2 is connected to the top of the package substrate 1 using BGA (ball grid array) connection, and the multi-layered chip capacitors 4 are connected to the bottom surface of the package substrate 1 via solder bumps. The package substrate 1 is also connected to the top of the circuit wiring board (mother board) 3 via solder bumps. The package substrate 1 is, for example, a multi-chip module (MCM) substrate.
As for the semiconductor device of FIG. 1, in order to avoid the interference of the height of the multi-layered chip capacitors 4 with the circuit wiring board 3, the portion of the circuit wiring substrate 3 where the capacitors 4 are mounted in opposing relationship to the substrate 3 must be cut through.
In this case, the inductance between the semiconductor IC chip 2 and the capacitors 4 poses the problem of power supply noise at high frequencies.
The semiconductor device, such as shown in FIG. 1, requires the wiring leads within the package substrate 1 to connect the multi-layered chip capacitors 4 and the semiconductor IC chip 2, and the wiring leads within the package substrate 1 have a significant inductance when the IC chip 2 operates at high frequencies. Even if the decoupling capacitors 4 are arranged therein, the effect of suppressing the fluctuation of the power-supply voltage to the IC chip 2 during high-speed operation and the effect of absorbing the high frequency ripple are fading.
What is needed for suppressing the variation of the power-supply voltage to the IC chip 2 is to reduce the equivalent in-series resistance (ESR) and the equivalent in-series inductance (ESL) of the capacitors 4. Especially there is a problem in that the increase in the inductance due to the wiring leads within the package substrate 1 deteriorates the high frequency characteristics of the decoupling capacitors 4.
In order to overcome the problem, reduction of the inductance is attained by positioning the capacitors as close as possible to the IC chip such that the length of the wiring leads from the power supply and the ground of the IC chip to the capacitors is made shortest.
Japanese Laid-Open Patent Application No. 4-211191 discloses a substrate with a built-in capacitor which is formed with a thin-film dielectric layer and conductive layers on a ceramic wiring substrate. The capacitor is devised to reduce the inductance, thereby realizing reduction of the power supply noise.
Moreover, Japanese Laid-Open Patent Applications No. 7-176453, No. 2001-68583 and No. 2001-35990 disclose some thin-film decoupling capacitors. In such capacitor configurations, the upper surface pads of the capacitor formed on the carrier substrate having the via holes are connected to the semiconductor IC chip, and the lower surface pads are connected to the circuit wiring substrate. The capacitor configurations are provided to reduce the inductance.
FIG. 2A and FIG. 2B show the structure of each of conventional semiconductor devices in which the interposer with a built-in capacitor is mounted.
In the configuration of FIG. 2A, the semiconductor IC chip 2 is connected to the top of the package substrate 1 using BGA connection, and the interposer 5 with the built-in capacitor is connected to the bottom of the IC chip 2 using BGA connection. In the configuration, to avoid the interference between the interposer 5 and the package substrate 1, the surface portion of the package substrate 1 where the interposer 5 is mounted is cut partially.
In the configuration of FIG. 2B, the semiconductor IC chip 2 is connected to the top of the interpose 5 with the built-in capacitor using BGA connection, and the interposer 5 is connected to the top of the package substrate 3 using BGA connection.
When compared with the semiconductor device of FIG. 1, the semiconductor devices of FIG. 2A and FIG. 2B have a shorter connection distance of the IC chip and the capacitor. However, if the interposer configuration is used, the number of production processes needed to manufacture the semiconductor devices will increase, and also the technical difficulty of the production may arise. This makes the low-cost production of the semiconductor devices difficult. Moreover, the number of interconnections between the components of the semiconductor devices increases, and the problem of reliability may arise.
Furthermore, in the case of the configuration of FIG. 2A, because of the thickness of the capacitor itself, it is necessary to perform machining to cut partially the portion of the package substrate before the IC chip is mounted on the package substrate.
Conventionally, in order to position the capacitor in close proximity to the IC chip, it has been necessary to use the interposer-type chip capacitor mounted between the carrier substrate and the IC chip as shown in FIG. 2A or FIG. 2B.
However, to prepare the interposer-type chip capacitor, the through vias in the substrate must be formed. In order to form the through vias, it is necessary to carry out the simultaneous baking process for the conductive material and the ceramic material, or carry out the forming of through holes in the substrate such as a silicon substrate, and the filling of the conductive material into the through holes of the substrate. Therefore, the technical difficulty of the production will arise, and it is difficult to attain the low-cost production of the semiconductor devices.